For many years, the market expectation for electronic components has been for continuing miniaturization. In an attempt to meet this expectation, designers and manufacturers of electronic components look for ways to decrease the spacing of transistors and other electronic devices on a chip. However, as electronic devices are brought into closer and closer proximity with each other, the problem of electronic interference between such devices becomes more pronounced. Deep trench isolation structures have been used to electrically isolate closely-spaced electronic devices on a chip, and deep trench processing is already common in such applications as dynamic random access memory (DRAM) and radio frequency (RE) combined bipolar and complementary metal-oxide semiconductor (BiCMOS) process flows. Yet existing processes for deep trench fabrication are not well suited to integration into a deep sub-micrometer shallow trench process when the deep trench is required to act as a high-voltage (approximately 50 volts and above) isolation structure. Such processes tend both to expose semiconductor wafers to excessive thermal budget and to interfere with or complicate the formation of shallow trench isolation (STI) structures. Accordingly, there exists a need for a method of manufacturing a high-voltage deep trench inside a shallow trench in deep sub-micrometer geometries, where the method of manufacturing reduces the thermal budget to which the semiconductor wafer is exposed and smoothly integrates the formation of deep trench structures into existing process modules with a minimal addition of new process steps. The manufacturing method should also be compatible with power integrated circuit (IC) technology, such that the manufactured semiconductor components which utilize the deep trench for isolation are capable of sustaining high voltages without breaking down.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the invention. Additionally, elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of embodiments of the present invention. The same reference numerals in different figures denote the same elements.
The terms “first,” “second,” “third,” “fourth,” and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms “comprise,” “include,” “have,” and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. The term “coupled,” as used herein, is defined as directly or indirectly connected in an electrical or non-electrical manner.